8bit Multiplier Verilog Code Github -

If you synthesize this code for a modern FPGA (like a Xilinx Artix-7 or Intel Cyclone V), you will observe an interesting phenomenon.

Instead of creating thousands of logic gates (LUTs), the synthesizer will likely report that it used a DSP Slice.

Modern FPGAs contain dedicated hard-blocks called DSPs (Digital Signal Processors) specifically designed for multiplication and accumulation. These blocks can perform $18 \times 18$ or $27 \times 18$ multiplication in a single clock cycle at very high frequencies (often > 300MHz). 8bit multiplier verilog code github

If you want to force the tool to use logic gates (LUTs) for educational purposes, you must add a synthesis constraint or attribute in the Verilog code:

(* use_dsp = "no" *) // Xilinx Specific Attribute
module multiplier_8bit(
    input [7:0] A,
    input [7:0] B,
    output [15:0] P
);
    assign P = A * B;
endmodule

No Verilog module is complete without a testbench. This code simulates the multiplier to verify it produces correct outputs. If you synthesize this code for a modern

`timescale 1ns / 1ps
module tb_multiplier_8bit;
// Inputs
    reg [7:0] A;
    reg [7:0] B;
// Outputs
    wire [15:0] P;
// Instantiate the Unit Under Test (UUT)
    multiplier_8bit uut (
        .A(A), 
        .B(B), 
        .P(P)
    );
integer i, j;
initial begin
        // Initialize Inputs
        A = 0;
        B = 0;
$display("Time\t A(Dec)\t B(Dec)\t Product(Dec)\t Status");
        $display("----------------------------------------------------");
// Test 1: Specific Edge Cases
        // Max value
        #10 A = 8'hFF; B = 8'hFF; // 255 * 255 = 65025
        #10 check_result(255, 255, 65025);
// Zero case
        #10 A = 8'h00; B = 8'hAA;
        #10 check_result(0, 170, 0);
// Powers of 2
        #10 A = 8'h01; B = 8'h01;
        #10 check_result(1, 1, 1);
#10 A = 8'h10; B = 8'h10; // 16 * 16 = 256
        #10 check_result(16, 16, 256);
// Test 2: Exhaustive Test (Loop)
        // Note: 256*256 = 65,536 iterations. 
        // This might take a moment in simulation but ensures 100% coverage.
$display("Starting Exhaustive Test...");
        for (i = 0; i < 256; i = i + 1) begin
            for (j = 0; j < 256; j = j + 1) begin
                A = i;
                B = j;
                #1; // Small delay for propagation
                if (P !== (i * j)) begin
                    $display("ERROR: A=%d, B=%d, Expected=%d, Got=%d", i, j, i*j, P);
                    $finish;
                end
            end
        end
$display("All Tests Passed!");
        $finish;
    end
// Task for checking specific cases easily
    task check_result;
        input [7:0] val_a;
        input [7:0] val_b;
        input [15:0] expected;
        begin
            if (P === expected)
                $display("%0t\t %d\t %d\t %d\t PASS", $time, val_a, val_b, P);
            else
                $display("%0t\t %d\t %d\t %d\t FAIL (Expected %d)", $time, val_a, val_b, P, expected);
        end
    endtask
endmodule

module top_multiplier #(
    parameter ARCH_TYPE = "ARRAY"  // "ARRAY", "CARRY_SAVE", "WALLACE"
)(
    input  wire        clk,
    input  wire        rst_n,
    input  wire [7:0]  A,
    input  wire [7:0]  B,
    input  wire        start,
    output reg [15:0]  P,
    output reg         done
);

wire [15:0] product;
generate
    if (ARCH_TYPE == "ARRAY") begin
        multiplier_array u_mult (
            .A(A), .B(B), .P(product)
        );
    end else if (ARCH_TYPE == "CARRY_SAVE") begin
        multiplier_carry_save u_mult (
            .A(A), .B(B), .P(product)
        );
    end else begin
        multiplier_wallace u_mult (
            .A(A), .B(B), .P(product)
        );
    end
endgenerate
// Pipeline register for product output
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        P <= 16'b0;
        done <= 1'b0;
    end else if (start) begin
        P <= product;
        done <= 1'b1;
    end else begin
        done <= 1'b0;
    end
end



endmodule

This project is licensed under the MIT License - see the LICENSE file for details.

When searching "8bit multiplier verilog code github", you'll encounter results with varying quality. Here's how to evaluate them: No Verilog module is complete without a testbench

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