Because ICC is a mature tool (the last major releases were in the L-2016.03 to 2018.06-SP range), the community support found on forums like Reddit or Stack Exchange is dwindling. Synopsys's official SolvNetPlus remains the primary resource, but navigating it requires a support contract.
However, the Synopsys ICC User Guide PDF remains relevant for three key reasons:
The Synopsys ICC (IC Compiler) User Guide is a foundational document for physical design engineers working on complex integrated circuits. ICC is a flagship place-and-route tool used for netlist-to-GDSII implementation, and its user guide provides comprehensive instructions on how to control the tool’s features.
Key Contents of the Guide:
How to Access the Official PDF: Since this document is copyrighted and proprietary to Synopsys (now part of the broader Synopsys EDA suite, though ICC has largely been succeeded by Fusion Compiler and IC Compiler II), the PDF is not legally available on public open-source platforms.
To obtain the genuine Synopsys ICC User Guide (in PDF format):
Through a Licensed Workstation:
icc -doc to open a browser-based documentation index.Synopsys Learning Center:
Important Note on Version Compatibility:
Alternative (For Learning Only – Unofficial):
Summary Recommendation: If you have a valid Synopsys license, log into SolvNet. If you do not have access, contact your university or company's EDA administrator. The ICC User Guide PDF is a critical resource, but it is legally restricted to licensed users only.
This guide provides a foundational overview of the Synopsys IC Compiler (ICC) physical design flow based on standard industry tutorials and official documentation. 1. Environment & Setup
Before launching the tool, ensure your UNIX/Linux environment is correctly configured with the necessary technology libraries and design files.
Startup Commands: Launch the tool using icc_shell. To enable the graphical interface, use icc_shell -gui or type gui_start within the shell.
Library Creation: Create a Milkyway (or NDM for ICC II) design library to store your design data using the create_mw_lib command. synopsys icc user guide pdf
Data Import: Load your synthesized Verilog netlist (import_designs) and read the Design Constraints file (read_sdc) to define timing requirements. 2. The Physical Design Flow
The standard flow follows a sequential path from floorplanning to final verification:
Floorplanning (create_floorplan): Define the core area, aspect ratio, and I/O pin placement. This stage establishes the physical boundaries of your chip.
Power Planning: Create power and ground networks. Common commands include derive_pg_connection for logical connections and create_rectangular_rings / create_power_straps for the physical mesh.
Placement (place_opt): Automatically place standard cells within the core while optimizing for timing and congestion.
Clock Tree Synthesis (clock_opt): Build the clock distribution network to minimize skew and insertion delay.
Routing (route_opt): Perform global and detailed routing to connect all signals. This is often the most time-intensive step.
Filler Cell Insertion: Fill empty gaps between standard cells to ensure electrical continuity using insert_stdcell_filler. 3. Verification & Export
Once routing is complete, you must verify the design before signoff.
DRC & LVS: Check for Design Rule Violations (verify_drc) and verify that the layout matches the schematic (verify_lvs).
Timing Analysis: Use report_timing at various stages to ensure the design meets its slack requirements.
GDSII Export: Export the final layout for manufacturing using write_stream. Additional Resources
For full official manuals, users typically access the Synopsys SolvNetPlus portal or the local installation directory (e.g., [INSTALL_DIR]/doc/icc/iccug.pdf). You can also find detailed community-provided guides on platforms like Scribd and SlideShare. ICC Tutorial PDF | PDF | Science & Mathematics - Scribd
The Synopsys IC Compiler (ICC/ICC2) user guide details the physical implementation process, covering placement, routing, and optimization to convert synthesized netlists into GDSII. Key sections focus on floorplanning, clock tree synthesis, and low-power, multivoltage design, utilizing TCL-based commands for ASIC design. For detailed user guides and tutorials, search platforms like Because ICC is a mature tool (the last
What is Synopsys ICC? Competitors, Complementary Techs & Usage 24 Nov 2025 —
The Synopsys IC Compiler (ICC) and its successor, IC Compiler II (ICC II), are the industry-leading solutions for physical implementation, covering everything from design planning to final signoff. The user guides for these tools are essential for mastering the complex flows of place-and-route (P&R). 📘 Core Documentation Overview
Synopsys provides several specialized guides depending on your stage in the design flow. You can find detailed versions like the IC Compiler™ II Multivoltage User Guide to manage complex power domains or the IC Compiler™ II Design Planning User Guide for early-stage floorplanning and hierarchy management. Key Manuals for Your Flow
Implementation User Guide (iccug): The primary manual describing the overall P&R flow.
Command Reference Guide: Detailed Tcl syntax for all ICC2 Useful Commands, such as report_timing and place_opt.
Multivoltage Flow Guide: Focuses on IEEE 1801 (UPF) support for low-power designs.
Data Model Guide: Explains the library and block structure used to store design data. 🚀 The IC Compiler Implementation Flow
The user guide typically breaks down the physical design process into several manageable phases: 1. Design Initialization
Library Setup: Loading technology files (TLU+) and physical libraries. Netlist Import: Reading the gate-level Verilog netlist.
Constraints: Applying SDC (Synopsys Design Constraints) for timing goals. 2. Design Planning & Floorplanning Defining the core and die area boundaries.
Placing macros (SRAMs, IPs) and creating power/ground rings.
You can learn the basics of this in an IC Compiler 1 Workshop module. 3. Placement & Optimization
place_opt: Automatically places standard cells while optimizing for timing and congestion.
Legalization: Ensuring all cells align perfectly with the site rows. 4. Clock Tree Synthesis (CTS) How to Access the Official PDF: Since this
clock_opt: Building the clock buffer tree to minimize skew and insertion delay.
Post-CTS Optimization: Fixing hold time violations introduced by the new clock tree. 5. Routing
Global Routing: Planning the general path of wires to avoid congestion.
Detail Routing: Finalizing the metal traces using the Zroute engine to meet DRC (Design Rule Check) requirements. 🛠️ How to Access Official Guides
For the most up-to-date and authorized PDFs, you should use official channels:
SolvNetPlus: Synopsys' primary support portal. Registered users can access the Quick Guide to SolvNet to learn how to download the latest Synopsys Documentation.
man Pages: While in the icc_shell, you can type man for instant help on specific Tcl commands.
Learning Paths: Explore curated Synopsys Learning Journeys for structured training on IC Compiler II.
💡 Key Tip: Use the write_script command in ICC to export your current session's settings into a Tcl script. This is often more helpful for debugging than the general user guide alone!
Are you currently working on a flat or hierarchical design, and are there specific violations (like timing or DRC) you're trying to solve? I can help you find the specific commands or flow steps to address them.
The Synopsys IC Compiler (ICC) user guide outlines the physical design flow, covering design setup, floorplanning, placement, clock tree synthesis, routing, and timing analysis. It serves as a comprehensive manual for transforming netlists into layouts, with specific versions available for ICC II and its multi-voltage capabilities. Access the official documentation for the most accurate information on Synopsys SolvNetPlus or explore community-hosted versions on platforms like
IC Compiler™ II Multivoltage User Guide | PDF | License - Scribd
Don't read the ICC UG cover to cover (it is ~1,500 pages). Use these search tricks:
If you have ICC installed on a Linux server, the PDF is almost certainly already on your hard drive. Navigate to:
$SYNOPSYS_ICC_HOME/doc/icc_ug/icc_ug.pdf
You can often open this directly with evince or acroread in your terminal.
This is the most common confusion. Synopsys discontinued the original IC Compiler (ICC) in favor of IC Compiler II (ICC2) around 2014-2016.