Verigy 93k Tester Manual
Before operating, you must understand the physical hierarchy. The manual typically breaks the system down as follows:
The 93K is a modular, scalable tester. A manual for a base configuration (e.g., 128 digital channels, 4 PS1600 power supplies) looks vastly different from a system with 1024 channels, RF modules, and high-speed optical I/O.
The 93K uses burst tables to sequence patterns. The manual explains:
The 93K can test 16, 32, or even 128 sites in parallel. The manual details:
The manual includes chapters on:
If you have any more details about the Verify 93k tester, such as its application or any specific functions you're trying to use, I could try to provide more tailored advice.
The Verigy V93000 (V93K) platform stands as a cornerstone in the semiconductor industry, recognized as a highly scalable System-on-Chip (SoC) test platform designed to handle everything from engineering characterization to high-volume manufacturing. Its documentation serves as the essential roadmap for test engineers, detailing a complex architecture built on "test processor-per-pin" technology. 1. Hardware Architecture and Configuration
The V93000 SoC series hardware manual provides a deep dive into its modular structure. Key sections typically cover:
System Classes: The documentation distinguishes between different classes (e.g., A, C, S, and L), which vary in test head size to match specific pin-count and performance requirements. verigy 93k tester manual
Core Components: It outlines the water-cooling technology essential for maintaining thermal stability during high-speed tests, the card cage structure, and the pogo block interfaces that connect the tester to the device under test (DUT).
Instrument Modules: Detailed specifications are provided for digital channels (like the Pin Scale 800), Device Power Supplies (DPS), and specialized subsystems like the Wave Scale RF for high-frequency wireless testing. 2. Software and Programming with SmarTest
Central to the manual is the SmarTest software overview, which guides users through the Eclipse-based integrated development environment (IDE).
Test Development: The manual instructs on setting up test flows, defining pin configurations, levels, and timing.
RDI and C++ Coding: Engineers learn to use Rapid Development Instruction (RDI) APIs to write custom C++ test methods for complex digital and DC tests.
Debugging Tools: A significant portion is dedicated to "Shmoo" plots, pin margin tools, and pattern debuggers used to solve fail modes during characterization. V93000｜SoC Test Systems｜ADVANTEST CORPORATION
The Verigy V93000 (now Advantest) is a high-performance system-on-a-chip (SoC) tester. While the official full manual is proprietary and typically accessed through the Advantest Technical Documentation Center (TDC), this guide outlines the standard operating procedures and manual testing workflows for engineers. 1. Hardware System Overview
Before starting, verify the physical configuration of the V93000 platform. Before operating, you must understand the physical hierarchy
Test Head: Contains the pin electronics and card cages. Ensure it is properly docked (hard docked) to the DUT (Device Under Test) loadboard.
Workstation: Usually runs Red Hat Enterprise Linux (RHEL) to host the SmarTest software.
Infrastructure: Check water cooling status for high-power systems or compressed air for specific HSIO (High-Speed I/O) modules. 2. Software Setup (SmarTest 8)
Manual testing is primarily conducted through the SmarTest 8 environment. AT93000 System User Manual - Multilane
Verigy (now Advantest) V93000 (93k) tester manuals are primarily distributed through Advantest's proprietary portals, but several technical guides and reference manuals are available through authorized partners or archive sites. Official Documentation Center The primary source for all current V93000 manuals is the Advantest Technical Documentation Center (TDC) Requires a service agreement and a myAdvantest portal
Includes the SmarTest help system, hardware specifications, and maintenance guides. AI Support:
The TDC now features an AI-powered assistant to help engineers find specific step-by-step guidance through natural language queries. ADVANTEST CORPORATION SmarTest Software & Programming Guides SmarTest Overview:
A detailed breakdown of the software environment used to control the tester, including pin configuration, level setup, and timing. SmarTest 7 Digital Training: Documentation for the Smart Scale Performance Board (PB) / Load Board: The custom
series, covering test flow, calibration, and debugging tools like Shmoo plots. Device License Lab: For software administration, the V93000 Device License Lab Guide provides instructions on using the
license management utility and starting SmarTest in offline mode. Hardware & System Reference Hardware Overview:
Covers the SOC tester platform architecture, water cooling technology, and card cage structure. System Reference: Includes detailed material on system start-up and shutdown
, DUT board mechanical design, and analog module restrictions. Direct-Probe™ Manuals:
Documentation for wafer-stage testing and signal integrity maintenance. Utah Nanofab Third-Party & Auxiliary Guides user guides - CMC Microsystems
The Verigy (now ) V93000 (V93K) is a modular, high-speed automated test equipment (ATE) system designed for System-on-a-Chip (SoC) semiconductor testing. Accessing the official manuals requires the Advantest Technical Documentation Center (TDC)
, a standalone help application that provides searchable content, including hardware specs, software guides, and safety ratings. Verigy 93K Hardware Architecture
The system is built on a scalable platform consisting of several key components:
93k Tester 02 Hardware Overview Rev.7.2.2.A.00 | PDF - Scribd